1. Field of the Invention
The present invention relates to a protection diode for protecting an internal circuit from external static electricity, to a semiconductor integrated circuit device having such a protection diode, to a method of assembling such a semiconductor integrated circuit device, and to an electronic product having such a semiconductor integrated circuit device.
2. Description of the Prior Art
A semiconductor integrated circuit chip has a plurality of pads formed on the surface thereof for connection with another semiconductor integrated circuit chip or other device, and exchange of signals between such an external device and the internal circuit of the semiconductor integrated circuit chip mentioned first is achieved via those pads. When this semiconductor integrated circuit chip is used singly, the pads thereof are connected to a lead frame that leads to the outside of the package, and the entire chip is sealed in a resin mold.
A semiconductor integrated circuit chip is, after a diffusion process and before an assembly process, subjected to inspection, with a probe put on various spots on the wafer substrate, usually on pads formed thereon as described above. During this inspection, and whenever the semiconductor integrated circuit chip is handled unconnected after assembly, it is liable to receive an excessive voltage as resulting from static electricity from the probe or the lead frame. Such an excessive voltage, if applied to the internal circuit via the pads, causes destruction of the internal circuit.
For this reason, as shown in FIG. 5, a MOS IC is usually provided with protection diodes that constitute a protection circuit. A pad 2 formed on a semiconductor integrated circuit chip 1 is connected to an internal circuit 7 by way of a conductor 3. On the conductor 3, near the pad 2, a protection circuit 6 is provided that is composed of diodes 4 and 5.
Exchange of signals with the internal circuit 7 is achieved via the pad 2 by way of the conductor 3. The protection circuit 6 is provided to protect the internal circuit 7 when an excessive voltage is applied from outside of the semiconductor integrated circuit chip 1.
Across the diodes 4 and 5 constituting the protection circuit 6, there exist parasitic capacitances 8 and 9 due to the junction capacitances that appear at junctions produced by diffusion. These parasitic capacitances 8 and 9 act not only to increase electric power consumption but also, in a device such as a CPU or an image processing chip for a personal computer, to impose a limit on the processing rate of the device.
For example, suppose that the parasitic capacitance of a protection diode is 5 pF. Then, in a semiconductor integrated circuit chip operating from a 3.3 V source, the delay time and the transient current are evaluated as described below on the basis of the following formula:
T=C/R=Cxc2x7E/I
where
T represents the time constant,
C represents the capacitance,
R represents the resistance,
E represents the voltage (the amplitude of the signal), and
I represents the transient current.
Specifically, if it is assumed that the delay time is 1 ns, a transient current of 16.5 xcexcA needs to be supplied, and thus electric power consumption increases accordingly. This delay time results from a single protection diode. That is, in cases where, as in a multichip IC, the pads of two IC chips are connected together with solder bumps or wires as will be described later, a transient current of 33 xcexcA, i.e. twice the current given just above, needs to be supplied.
In addition, a delay of 1 ns corresponds to a 10% delay in a semiconductor integrated circuit chip operating at 100 MHz, which is not a degree of delay that can be ignored. Given that faster processing rates are generally welcomed in many devices, parasitic capacitances pose a serious problem by preventing achievement of higher processing rates and of lower electric power consumption.
FIG. 6 is a diagram showing chip-on-chip mounting using solder bumps as is commonly practiced today. On a semiconductor integrated circuit chip 1, another semiconductor integrated circuit chip 10 is mounted in such a way that the two chips face each other. Then, their pads are connected together with solder bumps 11. Here, each pad is provided with a protection circuit 6 as shown in FIG. 5. However, in mounting as shown in FIG. 6, connection is achieved in a way as shown in FIG. 7, and therefore there is no risk of an excessive voltage being applied to the pads from the outside. Accordingly, the protection circuits 6 do not necessarily have to be provided.
However, in reality, even in a case like this where no protection circuit is necessary, protection circuits 6 are provided which are each accompanied by parasitic capacitances as shown in FIG. 5 that cause the problem described above. It is possible, with mounting as shown in FIG. 6 in mind, to produce semiconductor integrated circuit chips having no protection circuit provided for their pads. This, however, is impractical because it increases the risk of the internal circuit being destroyed by application of an excessive voltage during an inspection or assembly process.
An object of the present invention is to provide a semiconductor integrated circuit device having a protection circuit that is effective in inspection and assembly processes but that permits a high processing rate in actual operation, and to provide a method of assembling such a semiconductor integrated circuit device.
To achieve the above object, according to one aspect of the present invention, in a semiconductor integrated circuit device having a protection circuit connected to an external connection pad of the semiconductor integrated circuit device so as to prevent an excessive voltage from being applied to an internal circuit that is connected to the external connection pad, a conductor for applying a voltage to the protection circuit is provided near the external connection pad in the form of a mount-assist pad that is short-circuited to the external connection pad during mounting.
This structure allows a voltage to be applied to the protection circuit by way of the conductor when, for example, the internal circuit is inspected via the external connection pad before mounting. During mounting after inspection, the mount-assist pad and the external connection pad are short-circuited together. This makes it possible to ignore the effect of the capacitances present, for example, across the diodes constituting the protection circuit. The mount-assist pad plays also an assisting role in mounting.
According to another aspect of the present invention, a semiconductor integrated circuit device is provided with:
a test pad to be touched with a probe during inspection;
an external connection pad connected to the test pad by way of a conductor;
first and second voltage application pads;
a first mount-assist pad connected to the first voltage application pad and provided near the external connection pad;
a second mount-assist pad connected to the second voltage application pad and provided near the external connection pad;
a first protection diode having one end connected to the first voltage application pad and having another end connected to the test pad; and
a second protection diode having one end connected to the second voltage application pad and having another end connected to the test pad.
In this structure, the test pad is used as the target to be touched with the test probe during inspection. At this time, the test pad is connected to the internal circuit via the external connection pad. However, since the first and second protection diodes are at one end connected to this test pad and at the other end connected to the first and second voltage application pads respectively, there is no risk of the internal circuit being destroyed by an excessive voltage (whether the voltage is positive or negative) received from the outside via the test pad. On the other hand, during mounting using, for example, a solder bump, the first and second mount-assist pads and the first and second voltage application pads, all formed near the external connection pad, are short-circuited to the external connection pad. Thus, after mounting, both ends of each of the first and second protection diodes are kept substantially at identical potentials, and therefore the parasitic capacitances that accompany them do not exert any effect. This makes it possible to achieve a higher processing rate and lower electric power consumption in the semiconductor integrated circuit device as a whole. Here also, the first and second mount-assist pads play an assisting role in mounting.